1. Field of the Invention
This invention relates in general to Peripheral Component interconnect (PCI) busmaster devices, and more particularly, to busmaster devices with enhanced command processing capability, which reduces both host processor loading and PCI device processor loading.
2. Description of Related Art
Today's computing systems have seen several decades of evolution. Evolution which has transformed one-of-a-kind, custom built machines into common, everyday appliances found in most homes today. Central processing units (CPU) which were the size of refrigerators, requiring many kilowatts (kW) of power and associated cooling, have been reduced to printed circuit board (PCB) implementations, which have proliferated the computing industry. The relatively few peripherals operated in combination with the early CPUs Including tape readers, teletypes. Sine printers, etc., were tightly coupled to the early CPUs, which yielded highly customized computing solutions.
The integrated circuit (IC) Is largely, if not wholly, responsible for the drastic reduction in the size and power requirements of the early computing solutions. In addition, the IC is largely responsible for the exponential increase in the computational capabilities of the modern day desktop computer. Through the development of the IC, not only has the CPU been reduced to printed circuit board implementations, but so have peripherals such as Random Access Memory (RAM), high resolution graphics, full motion video drivers and high bandwidth networking cards, to name only a few. Each of the peripheral applications implemented on PCB's share a common communication architecture with the CPU called the computer bus.
The computer bus allows communication between the CPU, or processor, and its peripherals. The computer bus is generally separated into several functional groups such as address, data and control. The address group of the computer bus identifies the specific peripheral attached to the computer bus as well as a particular component contained within the peripheral, such as a register or memory location. The data group of the computer bus defines the information transferred to or received from the peripheral. The control group of the computer bus defines the method or protocol used to effect data or control transfers on the computer bus.
Contemporary computer buses operate in a synchronous fashion, such that all transactions on the computer bus occur synchronously with a rising or failing edge of a master bus clock. The master bus clock, however, is typically slower than the speed of the processor attached to the bus, creating a performance bottleneck at the computer bus level. Subsequently, computer bus speeds have increased in order to reduce the performance bottleneck, but increasing computer bus speeds requires reduced computer bus lengths in order to control propagation delay. Performance of the computer bus is also limited by the number of peripheral devices attached to the computer bus. The number of peripheral devices attached to the contemporary computer bus increases the effective capacitance of the computer bus, adversely effecting computer bus transfer rates.
One of the earlier computer buses, Industry Standard Architecture (ISA), established itself as an evolutionary enhancement of the time, being well matched to processor performance and peripheral requirements of the early personal computers (PCs). The ISA computer bus, however, soon fell victim to the increasing performance demands of graphical computing, in addition, the ISA peripherals used wire jumpers and Dual In-line Package (DIP) switches to resolve input/Output (I/O) addresses, interrupt and Direct Memory Access channel allocation, which proved to be labor intensive for the personal computer consumer.
The Video Electronics Standards Association Local (VL) bus, provided a subsequent attempt to overcome the limitations of the ISA computer bus architecture. The VL bus strategy is to attach, for example, a video controller, as well as other high bandwidth peripheral devices, directly to the processor's local bus, equating the bus speed of the peripheral device attached to the VL bus to that of the processor's bus speed. The VL bus was successful to increase the bus speeds of the peripheral devices, however, the VL bus exhibited its own shortcomings, such as a severe limitation on the number of VL bus peripheral devices allowed to operate on the VL bus. In addition, VL bus peripheral devices were necessarily processor dependent.
The Peripheral Component Interconnect (PCI) bus has been developed to provide coherence and standardisation, improving upon the ISA and VL bus limitations. The PCI bus specification first appeared in 1992, with subsequent revisions published in 1993, 1995 and 1999. The PCI bus specification provides several features, which potentially allows PCI implementations to accommodate computer architectures for many years to come. PCI bus transfer rates, for example, allow for hundreds of megabytes (MB) of data to be transferred per second. Any peripheral device attached to the PCI bus can become a bus master, responsible for initiating transactions on the PCI bus, thus reducing overhead workload for the processor. The PCI bus is processor independent, such that peripheral devices attached to the PCI bus need only comply with the PCI bus specification to be operable, regardless of the specific processor being used. PCI implementations allow peripheral devices that are newly introduced to the computing architecture to be automatically configured, the automatic configuration process is more commonly referred to as plug and play. The PCI bus, however, along with its ISA and VL bus predecessors, limits the number of peripheral devices that can share a particular PCI bus segment. In order to accommodate multiple PCI peripheral devices and even to accommodate a mixture, for example, of PCI and ISA bus compatible peripheral devices, PCI bridging is used.
PCI bridging allows for expansion of the PCI bus, such that multiple PCI peripheral devices can operate on the PCI bus, but are separated into their own PCI bus segments and then bridged to allow access to the PCI bus. Several types of bridges exist, for example, such as the PCI-to-PCI, Host-to-PCI and PCI-to-legacy bus bridges. The PCI-to-PCI bridge allows multiple PCI bus segments to be interconnected, such that each segment allows a fixed number of PCI peripheral devices to be connected to the PCI bus. The Host-to-PCI bridge, or commonly referred to as the north bridge, allows the host processor to access the PCI bus, because most host processors do not provide their own PCI bus interface adapter. Finally, the PCI-to-legacy bridges, or south bridge, allows legacy systems, such as an ISA peripheral device, to access the PCI bus. Many personal computers, for example, provide hard drive data storage and I/O peripheral devices on the ISA bus, which require a PCI-to-ISA bridge for proper operation in a PCI bus implementation.
PCI bus communication protocol establishes command transfers to be conducted synchronously with a master bus clock. That is to say, that the PCI bus master clock provides the clocking signal, used in combination with other bus handshake signals, to initiate, perform and terminate a command transfer between the host processor and PCI peripheral devices. As with any synchronous command transfer on the PCI bus, only one master and one target device have control of the PCI bus at any given time. The host processor, for example, acting as a bus master, seizes the PCI bus, places a target on the address bus and a bus command on the command bus on a first rising edge of the master bus clock. All targets listening on the PCI bus latch the address and command at a second rising edge of the master bus clock. Only one target on the PCI bus can claim ownership of the command and, after a given latency period, acknowledges its ownership of the command with subsequent support of the rest of the transaction. The latency period during the host to target command transaction on the PCI bus establishes unnecessary overhead constraints on the host processor. The overhead constraints adversely affect the host processor's efficiency, which ultimately reduces the speed of operation of the PCI bus system.
PCI devices often incorporate their own processor as well, in order to carry out functions specific to the particular PCI device. Prior art PCI devices, in PCI bus communication with the host processor, often experience latency periods during the course of PCI bus command sequencing, which establish unnecessarily high loading on the PCI device processor as well. An intermediate messaging unit, established within the PCI device, responsible for direct messaging to the processor memory, would be operative to reduce the loading on both the host processor and PCI device processor as well.
It can be seen that there is a need for a method and apparatus that handles message transfers between a host processor memory and a PCI device without the direct intervention of either host or PCI device processors.
It can be seen that there is a need for a method and apparatus that handles message transfers directly from host processor memory to release both the host processor and PCI device processor from unnecessary PCI bus transaction overhead.
It can be seen that there is a need for a method and apparatus that frees the host and PCI device processors to perform other critical functions and that increases the overall efficiency of operation of the PCI bus implementation.